The VLSI Handbook

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The

VLSI

Handbook Second Edition

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The Electrical Engineering Handbook Series Series Editor

Richard C. Dorf University of California, Davis

Titles Included in the Series The Handbook of Ad Hoc Wireless Networks, Mohammad Ilyas The Avionics Handbook, Second Edition, Cary R. Spitzer The Biomedical Engineering Handbook, Third Edition, Joseph D. Bronzino The Circuits and Filters Handbook, Second Edition, Wai-Kai Chen The Communications Handbook, Second Edition, Jerry Gibson The Computer Engineering Handbook, Vojin G. Oklobdzija The Control Handbook, William S. Levine The CRC Handbook of Engineering Tables, Richard C. Dorf The Digital Avionics Handbook, Second Edition Cary R. Spitzer The Digital Signal Processing Handbook, Vijay K. Madisetti and Douglas Williams The Electrical Engineering Handbook, Second Edition, Richard C. Dorf The Electric Power Engineering Handbook, Leo L. Grigsby The Electronics Handbook, Second Edition, Jerry C. Whitaker The Engineering Handbook, Third Edition, Richard C. Dorf The Handbook of Formulas and Tables for Signal Processing, Alexander D. Poularikas The Handbook of Nanoscience, Engineering, and Technology, William A. Goddard, III, Donald W. Brenner, Sergey E. Lyshevski, and Gerald J. Iafrate The Handbook of Optical Communication Networks, Mohammad Ilyas and Hussein T. Mouftah The Industrial Electronics Handbook, J. David Irwin The Measurement, Instrumentation, and Sensors Handbook, John G. Webster The Mechanical Systems Design Handbook, Osita D.I. Nwokah and Yidirim Hurmuzlu The Mechatronics Handbook, Robert H. Bishop The Mobile Communications Handbook, Second Edition, Jerry D. Gibson The Ocean Engineering Handbook, Ferial El-Hawary The RF and Microwave Handbook, Mike Golio The Technology Management Handbook, Richard C. Dorf The Transforms and Applications Handbook, Second Edition, Alexander D. Poularikas The VLSI Handbook, Second Edition, Wai-Kai Chen

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Edited by

Wai-Kai Chen University of Illinois Chicago, USA

Boca Raton London New York

CRC Press is an imprint of the Taylor & Francis Group, an informa business

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CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2007 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S. Government works Printed in the United States of America on acid-free paper 10 9 8 7 6 5 4 3 2 1 International Standard Book Number-10: 0-8493-4199-X (Hardcover) International Standard Book Number-13: 978-0-8493-4199-1 (Hardcover) This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use. No part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, please access www.copyright.com (http:// www.copyright.com/) or contact the Copyright Clearance Center, Inc. (CCC) 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. CCC is a not-for-profit organization that provides licenses and registration for a variety of users. For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged. Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe.

Library of Congress Cataloging-in-Publication Data The VLSI handbook / edited by Wai-Kai Chen.—2nd ed. p. cm.—(Electrical engineering handbook series; 38) Includes bibliographical references and index. ISBN 0-8493-4199-X 1. Integrated circuits—Very large scale integration. I. Chen, Wai-Kai, 1936- II. Title. III. Series. TK7874.75.V573 2006 621.39´5—dc22

Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com

2006050477

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Preface

We are most gratified to find that the first edition of The VLSI Handbook (2000) was well received and is widely used. Thus, we feel that our original goal of providing in-depth professional-level coverage of VLSI technology was, indeed, worthwhile. Seven years is a short time in terms of development of science and technology; however as this handbook shows, momentous changes have occurred during this period, necessitating not only the updating of many chapters of the handbook, but more startling, the addition and expansion of many topics. Significant examples are low-power electronics and design, testing of digital systems, VLSI signal processing, and design languages and tools to name a few of the more prominent additions.

Purpose The VLSI Handbook provides in a single volume a comprehensive reference work covering the broad spectrum of VLSI technology. It is written and developed for practicing electrical engineers in industry, government, and academia. The goal is to provide the most up-to-date information in integrated circuits (IC) technology, devices and their models, circuit simulations, low-power electronics and design, amplifiers, analog and logic circuits, memory, registers and system timing, microprocessor and ASIC, test and testability, design automation, VLSI signal processing, and design languages and tools. The handbook is not an all-encompassing digest of everything taught within an electrical engineering curriculum on VLSI technology. Rather, it is the engineer’s first choice in looking for a solution. Therefore, full references to other sources of contributions are provided. The ideal reader is a BS level engineer with a need for a one-source reference to keep abreast of new techniques and procedures as well as review standard practices.

Background The handbook stresses fundamental theory behind professional applications. To do so, it is reinforced with frequent examples. Extensive development of theory and details of proofs have been omitted. The reader is assumed to have a certain degree of sophistication and experience. However, brief reviews of theories, principles, and mathematics of some subject areas are given. These reviews have been done concisely with perception. The handbook is not a textbook replacement, but rather a reinforcement and reminder of material learned as a student. Therefore, important advancement and traditional as well as innovative practices are included. Since most of the professional electrical engineers graduated before powerful personal computers were widely available, many computational and design methods may be new to them. Therefore, computers and software use are thoroughly covered. Not only does the handbook use traditional references to cite sources for the contributions, but it also contains all relevant sources of information and tools that would

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Preface

assist the engineer in performing his/her job. This may include sources of software, databases, standards, seminars, conferences, etc.

Organization Over the years, the fundamentals of VLSI technology have evolved to include a wide range of topics and a broad range of practice. To encompass such a wide range of knowledge, the handbook focuses on the key concepts, models, and equations that enable the electrical engineer to analyze, design, and predict the behavior of very large-scale integrated circuits. While design formulas and tables are listed, emphasis is placed on the key concepts and theories underlying the applications. The information is organized into 13 major sections, which encompass the field of VLSI technology. Each section is divided into chapters, each of which is written by a leading expert in the field to enlighten and refresh knowledge of the mature engineer, and to educate the novice. Each section contains introductory material, leading to the appropriate applications. To help the reader, each article includes two important and useful categories: defining terms and references. Defining terms are key definitions and the first occurrence of each term defined is indicated in italic type in the text. The references provide a list of useful books and articles for further reading and for additional information on the topic.

Locating Your Topic Numerous avenues of access to information contained in the handbook are provided. A complete table of contents is presented at the beginning of the book. In addition, an individual table of contents precedes each of the 13 sections. Finally, each chapter begins with its own table of contents. The reader is urged to review these tables of contents to become familiar with the structure, organization, and content of the book. For example, see Section VIII: Microprocessor and ASIC, then Chapter 64: Microprocessor Design Verification, and then Section 64.2: Design Verification Environment. This tree-like structure enables the reader to move up the tree to locate information on the topic of interest. A combined subject and author index has been compiled to provide means of accessing information. It can also be used to locate definitions; the page on which the definition appears for each key defining term is given in this index. The VLSI Handbook is structured to provide answers to most inquiries and to direct inquirer to further sources and references. We trust that it will meet your needs.

Acknowledgments The compilation of this book would not have been possible without the dedication and efforts of the section editors, the publishers, and most of all the contributing authors. I wish to thank all of them and also my wife, Shiao-Ling, for her patience and understanding. Wai-Kai Chen Editor-in-Chief

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Editor-in-Chief

Wai-Kai Chen is professor and head emeritus of the Department of Electrical Engineering and Computer Science at the University of Illinois at Chicago. He received his BS and MS in electrical engineering from Ohio University, where he was later recognized as a distinguished professor. He earned his PhD in electrical engineering from the University of Illinois at Urbana-Champaign. Professor Chen has extensive experience in education and industry and is very active professionally in the fields of circuits and systems. He has served as visiting professor at Purdue University, University of Hawaii at Manoa, and Chuo University in Tokyo, Japan. He was editor of the IEEE Transactions on Circuits and Systems, Series I and II, president of the IEEE Circuits and Systems Society, and is the founding editor and editor-in-chief of the Journal of Circuits, Systems and Computers. He received the Lester R. Ford Award from the Mathematical Association of America, the Alexander von Humboldt Award from Germany, the JSPS Fellowship Award from Japan Society for the Promotion of Science, the National Taipei University of Technology Distinguished Alumnus Award, the Ohio University Alumni Medal of Wai-Kai Chen Merit for Distinguished Achievement in Engineering Education, the Senior University Scholar Award and the 2000 Faculty Research Award from University of Illinois at Chicago, and the Distinguished Alumnus Award from the University of Illinois at Urbana-Champaign. He is also the recipient of the Golden Jubilee Medal, the Education Award, the Meritorious Service Award from IEEE Circuits and Systems Society, and the Third Millennium Medal from the IEEE. He has also received more than a dozen honorary professorship awards from major institutions in Taiwan and China. A fellow of the Institute of Electrical and Electronics Engineers and the American Association for the Advancement of Science, Professor Chen is widely known in the profession for his published works which include Applied Graph Theory (North-Holland), Theory and Design of Broadband Matching Networks (Pergamon Press), Active Network and Feedback Amplifier Theory (McGraw-Hill), Linear Networks and Systems (Brooks/Cole), Passive and Active Filters: Theory and Implements (John Wiley), Theory of Nets: Flows in Networks (Wiley-Interscience), The Circuits and Filters Handbook (CRC Press), and The Electrical Engineering Handbook (Elsevier Academic Press).

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Contributors

Ramachandra Achar Department of Electronics Carleton University Ottawa, Ontario, Canada Arshad Ahmed DSP R&D Texas Instruments, Inc. Dallas, Texas Jonathan A. Andrews Department of Electrical and Computer Engineering Virginia Commonwealth University Richmond, Virginia James H. Aylor School of Engineering and Applied Science University of Virginia Charlottesville, Virginia R. Jacob Baker Department of Electrical and Computer Engineering University of Idaho at Boise Boise, Idaho Andrea Baschirotto Department of Innovation Engineering University of Lecce Lecce, Italy Charles R. Baugh C. R. Baugh and Associates Seattle, Washington

Magdy Bayoumi The Center for Advanced Computer Studies University of Louisiana Lafayette, Louisiana David Blaauw Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, Michigan Victor Boyadzhyan Jet Propulsion Laboratory Pasadena, California Alison Burdett Toumaz Technology Ltd. Abingdon, UK Wai-Kai Chen University of Illinois Chicago, Illinois Kuo-Hsing Cheng Tamkang University Tamkang, Taiwan

Amy Hsiu-Fen Chou National Tsing-Hua University Hsinchu, Taiwan Moon Jung Chung Department of Computer Science Michigan State University East Lansing, Michigan David J. Comer Department of Electrical and Computer Engineering Brigham Young University Provo, Utah Donald T. Comer Department of Electrical and Computer Engineering Brigham Young University Provo, Utah Daniel A. Connors Department of Computer Science University of Colorado Boulder, Colorado

Bi-Shiou Chiou Department of Electronics Engineering National Chiao Tung University Hsinchu, Taiwan

Donald R. Cottrell Silicon Integration Initiative, Inc. Austin, Texas

John Choma, Jr. Department of Electrical Engineering/Electrophysics University of Southern California Los Angeles, California

John D. Cressler School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, Georgia ix

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Sorin Cristoloveanu Institute of Microelectronics, Electromagnetism and Photonics Grenoble, France Wouter De Cock Katholieke Universiteit Leuven Leuven-Heverlee, Belgium Abhijit Dharchoudhury Motorola, Inc. Austin, Texas Robert P. Dick Department of Electrical Engineering and Computer Science Northwestern University Evanston, Illinois Vassil S. Dimitrov Department of Electrical and Computer Engineering University of Calgary Calgary, Alberta, Canada Donald B. Estreich Microwave Technology Division Agilent Technologies Santa Rosa, California John W. Fattaruso Texas Instruments, Inc. Dallas, Texas Ayman A. Fayed Texas Instruments, Inc. Dallas, Texas Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester Rochester, New York Shantanu Ganguly Intel Corporation Austin, Texas Aman Gayasen Department of Computer Science and Engineering Pennsylvania State University University Park, Pennsylvania

Contributors

Jan V. Grahn School of Information and Communication Technology KTH, Royal Institute of Technology Kista, Sweden Flavius Gruian Department of Computer Science Lund University Sweden Maria del Mar Hershenson Stanford University Stanford, California Charles Ching-Hsiang Hsu National Tsing-Hua University Hsinchu, Taiwan Jen-Sheng Hwang National Science Council Taipei, Taiwan Wen-mei W. Hwu University of Illinois at Urbana-Champaign Urbana, Illinois Kazumi Inoh Center for Semiconductor Research and Development Semiconductor Company Toshiba Corporation Yokohama, Japan Ali Iranli Electrical Engineering Department University of Southern California Los Angeles, California K. Irick Department of Computer Science and Engineering Pennsylvania State University University Park, Pennsylvania

M. J. Irwin Department of Computer Science and Engineering Pennsylvania State University University Park, Pennsylvania Hidemi Ishiuchi Center for Semiconductor Research and Development Semiconductor Company Toshiba Corporation Yokohama, Japan Mohammed Ismail Department of Electrical and Computer Engineering Ohio State University Columbus, Ohio Hiroshi Iwai Frontier Collaborative Research Center Tokyo Institute of Technology Yokohama, Japan Vikram Iyengar IBM Microelectronics Essex Junction, Vermont W. Kenneth Jenkins Department of Computer Science and Engineering Pennsylvania State University University Park, Pennsylvania Jeff Jessing Department of Electrical and Computer Engineering Boise State University Boise, Idaho Niraj K. Jha Department of Electrical Engineering Princeton University Princeton, New Jersey Graham A. Jullien Department of Electrical and Computer Engineering University of Calgary Calgary, Alberta, Canada

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Contributors

Dimitri Kagaris Department of Electrical and Computer Engineering Southern Illinois University Carbondale, Illinois Steve M. Kang University of California at Santa Cruz Santa Cruz, California Nick Kanopoulos Atmel Corporation Morrisville, North Carolina Naghmeh Karimi Electrical and Computer Engineering University of Tehran Tehran, Iran Tanay Karnik Strategic CAD Labs Intel Corporation Hillsboro, Oregon Yasuhiro Katsumata Engineering Planning Division Semiconductor Company Toshiba Corporation Kawasaki, Japan Ali Keshavarzi Circuit Research Labs Intel Corporation Hillsboro, Oregon Heechul Kim Department of Computer Science and Engineering Hankuk University of Foreign Studies Yongin, Kyung Ki-Do, Korea

Robert H. Klenke Department of Electrical and Computer Engineering Virginia Commonwealth University Richmond, Virginia Ivan S. Kourtev Department of Electrical and Computer Engineering University of Pittsburgh Pittsburgh, Pennsylvania Seok-Jun Lee DSP R&D Texas Instruments, Inc. Dallas, Texas Thomas H. Lee Stanford University Stanford, California Harry W. Li Formerly with the University of Idaho at Boise Yijun Li The Center for Advanced Computer Studies University of Louisiana Lafayette, Louisiana Chi-Sheng Lin Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan Frank Ruei-Ling Lin National Tsing-Hua University Hsinchu, Taiwan

Jihong Kim School of Computer Science and Engineering Seoul National University Seoul, Korea

Bin-Da Liu Department of Electrical Engineering National Cheng Kung University Tainan, Taiwan

Hideki Kimijima System LSI Division II Semiconductor Company Toshiba Corporation Kitakyushu, Japan

John Lockwood Department of Computer Science and Engineering Washington University St. Louis, Missouri

Stephen I. Long Department of Electrical and Computer Engineering University of California Santa Barbara, California Ashraf Lotfi Enpirion, Inc. Bridgewater, New Jersey B. Gunnar Malm School of Information and Communication Technology KTH, Royal Institute of Technology Kista, Sweden Mohammad Mansour Department of Electrical and Computer Engineering American University of Beirut Beirut, Lebanon Diana Marculescu Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, Pennsylvania Radu Marculescu Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, Pennsylvania Martin Margala Electrical and Computer Engineering Department University of Massachusetts Lowell, Massachusetts Shin-ichi Minato NTT Network Innovation Laboratories Kanagawa, Japan Shahrzad Mirkhani Electrical and Computer Engineering Department University of Tehran Tehran, Iran Sunderarajan S. Mohan Stanford University Stanford, California

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Hisayo S. Momose Center for Semiconductor Research and Development Semiconductor Company Toshiba Corporation Yokohama, Japan Eiji Morifuji System LSI Division I Semiconductor Company Toshiba Corporation Yokohama, Japan Toyota Morimoto Memory Division Semiconductor Company Toshiba Corporation Yokohama, Japan Saburo Muroga University of Illinois at Urbana-Champaign Urbana, Illinois Roberto Muscedere Research Centre for Integrated Microsystems (RCIM) University of Windsor Ontario, Canada Akio Nakagawa Discrete Semiconductor Division Semiconductor Company Toshiba Corporation Kawasaki, Japan Yuichi Nakamura NEC Corporation Kawasaki, Japan Michel S. Nakhla Department of Electronics Carleton University Ottawa, Ontario, Canada Zainalabedin Navabi Nanoelectronics Center of Excellence School of Electrical and Computer Engineering University of Tehran Tehran, Iran Philip G. Neudeck NASA Glenn Research Center Cleveland, Ohio

Contributors

C. Nicopoulos Department of Computer Science and Engineering Pennsylvania State University University Park, Pennsylvania

Patrick Reynaert Elektrotechniek, ESAT-MICAS Katholieke Universiteit Leuven Leuven-Heverlee, Belgium

Hideaki Nii System LSI Division I Semiconductor Company Toshiba Corporation Yokohama, Japan

Mahsan Rofouei Nanoelectronics Center of Excellence School of Electrical and Computer Engineering University of Tehran Tehran, Iran

Umit Y. Ogras Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, Pennsylvania

J. Gregory Rollins Antrim Design Systems Scotts Valley, California

Tatsuya Ohguro Center for Semiconductor Research and Development Semiconductor Company Toshiba Corporation Yokohama, Japan Mikael Östling School of Information and Communication Technology KTH, Royal Institute of Technology Kista, Sweden Seok-Bae Park Department of Electrical and Computer Engineering Ohio State University Columbus, Ohio Alice C. Parker Department of Electrical Engineering-Systems University of Southern California Los Angeles, California Massoud Pedram Electrical Engineering Department University of Southern California Los Angeles, California

Saeed Safari Nanoelectronics Center of Excellence School of Electrical and Computer Engineering University of Tehran Tehran, Iran Kirad Samavati Stanford University Stanford, California Naresh R. Shanbhag Electrical and Computer Engineering Department University of Illinois at Urbana-Champaign Urbana, Illinois Li Shang Department of Electrical and Computer Engineering Queen’s University Kingston, Ontario, Canada Rick Shih-Jye Shen National Tsing-Hua University Hsinchu, Taiwan Bing J. Sheu Taiwan Semiconductor Manufacturing Company Taiwan Dongkun Shin Samsung Electronics Co., LTD. Suwon, Korea

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Contributors

Muh-Tian Shiue Department of Electrical Engineering National Central University Chung-Li, Taiwan

T. Theocharides Department of Electrical and Computer Engineering University of Cyprus, Cyprus

Hamid Shojaei Electrical and Computer Engineering Department University of Tehran Tehran, Iran

Yosef Tirat-Gefen Department of Electrical Engineering-Systems University of Southern California Los Angeles, California

Bang-Sup Song Department of Electrical and Computer Engineering University of California San Diego, California

Chris Toumazou Institute of Biomedical Engineering University of London London, UK

Michiel Steyaert Katholieke Universiteit Leuven Leuven-Heverlee, Belgium

Spyros Tragoudas Department of Electrical and Computer Engineering Southern Illinois University Carbondale, Illinois

Earl E. Swartzlander, Jr. Department of Electrical and Computer Engineering University of Texas Austin, Texas Haruyuki Tago Toshiba Semiconductor Company Saiwai, Kawasaki, Japan Naofumi Takagi Department of Information Engineering Nagoya University Nagoya, Japan Emil Talpes Advanced Micro Devices, Inc. Sunnyvale, California Baris Taskin Department of Electrical and Computer Engineering Drexel University Philadelphia, Pennsylvania Donald C. Thelen American Microsystems, Inc. Bozeman, Montana

Yuh-Kuang Tseng Industrial Research and Technology Institute Hsinchu, Taiwan N. Vijaykrishnan Department of Computer Science and Engineering Pennsylvania State University University Park, Pennsylvania Suhrid A. Wadekar Department of Electrical Engineering-Systems University of Southern California Los Angeles, California Chorng-Kuang Wang Department of Electrical Engineering National Taiwan University Taipei, Taiwan R. F. Wassenaar Department of Electrical Engineering University of Twente The Netherlands

Louis A. Williams III Texas Instruments, Inc. Dallas, Texas Wayne Wolf Department of Electrical Engineering Princeton University Princeton, New Jersey Chung-Yu Wu Department of Electronics Engineering National Chiao Tung University Hsinchu, Taiwan Evans Ching-Song Yang National Tsing-Hua University Hsinchu, Taiwan Kazuo Yano System LSI Research Department Central Research Laboratory Hitachi Ltd. Kokubunji, Tokyo, Japan Ko Yoshikawa CAD Department Computers Division NEC Corporation Fuchu, Tokyo, Japan Kuniyoshi Yoshikawa Quality Promotion Center Semiconductor Company Toshiba Corporation Yokohama, Japan Takashi Yoshitomi System LSI Division I Semiconductor Company Toshiba Corporation Tokyo, Japan Min-Shueh Yuan Department of Electrical Engineering National Taiwan University Taipei, Taiwan C. Patrick Yue Stanford University Stanford, California

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Table of Contents

Preface ...................................................................................................................................... v Editor-in-Chief ...................................................................................................................... vii Contributors ........................................................................................................................... ix

SECTION I

VLSI Technology

1

Bipolar Technology B. Gunnar Malm, Jan V. Grahn and Mikael Östling ........................................................................................................... 1-3

2

CMOS/BiCMOS Technology

3

Silicon-on-Insulator Technology

4

SiGe HBT Technology

5

Silicon Carbide Technology

6

Passive Components

7

Power IC Technologies

8

Microelectronics Packaging

9

Multichip Module Technologies Victor Boyadzhyan and John Choma, Jr. ............................................................................................................... 9-1

Yasuhiro Katsumata, Tatsuya Ohguro, Kazumi Inoh, Eiji Morifuji, Takashi Yoshitomi, Hideki Kimijima, Hideaki Nii, Toyota Morimoto, Hisayo S. Momose, Kuniyoshi Yoshikawa, Hidemi Ishiuchi and Hiroshi Iwai ...................................................................................... 2-1 Sorin Cristoloveanu ................................................ 3-1

John D. Cressler ...................................................................... 4-1 Philip G. Neudeck .......................................................... 5-1

Ashraf Lotfi ............................................................................... 6-1 Akio Nakagawa ..................................................................... 7-1 Bi-Shiou Chiou .............................................................. 8-1

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SECTION II

Devices and Their Models

10

Bipolar Junction Transistor Circuits David J. Comer and Donald T. Comer............................................................................................................ 10-3

11

RF Passive IC Components

12

CMOS Fabrication

13

Analog Circuit Simulation

14

Interconnect Modeling and Simulation Michel S. Nakhla and Ramachandra Achar ....................................................................................................... 14-1

Thomas H. Lee, Maria del Mar Hershenson, Sunderarajan S. Mohan, Kirad Samavati and C. Patrick Yue ............................................... 11-1

SECTION III

Jeff Jessing ................................................................................. 12-1 J. Gregory Rollins ........................................................... 13-1

Low Power Electronics and Design

15

System-Level Power Management: An Overview Ali Iranli and Massoud Pedram ............................................................................................................ 15-3

16

Communication-Based Design for Nanoscale SoCs Umit Y. Ogras and Radu Marculescu............................................................................................................ 16-1

17

Power-Aware Architectural Synthesis Robert P. Dick, Li Shang and Niraj K. Jha ............................................................................................... 17-1

18

Dynamic Voltage Scaling for Low-Power Hard Real-Time Systems Jihong Kim, Flavius Gruian and Dongkun Shin ................................................................. 18-1

19

Low-Power Microarchitecture Techniques and Compiler Design Techniques Emil Talpes and Diana Marculescu ............................................... 19-1

20

Architecture and Design Flow Optimizations for Power-Aware FPGAs Aman Gayasen and Narayanan Vijaykrishnan................................................................................................ 20-1

21

Technology Scaling and Low-Power Circuit Design Ali Keshavarzi ................................................................................................................ 21-1

SECTION IV

Amplifiers

22

CMOS Amplifier Design Harry W. Li, R. Jacob Baker and Donald C. Thelen ........................................................................................................... 22-3

23

Bipolar Junction Transistor Amplifiers David J. Comer and Donald T. Comer............................................................................................................ 23-1

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24

High-Frequency Amplifiers Chris Toumazou and Alison Burdett ................................................................................................................ 24-1

25

Operational Transconductance Amplifiers

Mohammed Ismail, Seok-Bae Park, Ayman A. Fayed and R.F. Wassenaar .......................................................... 25-1

SECTION V

Logic Circuits

26

Expressions of Logic Functions

Saburo Muroga ..................................................... 26-3

27

Basic Theory of Logic Functions

28

Simplification of Logic Expressions

29

Binary Decision Diagrams Shin-ichi Minato and Saburo Muroga .............................................................................................................. 29-1

30

Logic Synthesis with AND and OR Gates in Two Levels Saburo Muroga .............................................................................................................. 30-1

31

Sequential Networks

32

Logic Synthesis with AND and OR Gates in Multi-Levels Yuichi Nakamura and Saburo Muroga .............................................................................. 32-1

33

Logic Properties of Transistor Circuits

34

Logic Synthesis with NAND (or NOR) Gates in Multi-Levels Saburo Muroga .............................................................................................................. 34-1

35

Logic Synthesis with a Minimum Number of Negative Gates Saburo Muroga .............................................................................................................. 35-1

36

Logic Synthesizer with Optimizations in Two Phases Ko Yoshikawa and Saburo Muroga ................................................................................... 36-1

37

Logic Synthesizer by the Transduction Method

38

Emitter-Coupled Logic

39

CMOS

40

Pass Transistors

41

Adders

42

Multipliers

Saburo Muroga ................................................... 27-1 Saburo Muroga............................................... 28-1

Saburo Muroga ....................................................................... 31-1

Saburo Muroga.......................................... 33-1

Saburo Muroga ........................... 37-1

Saburo Muroga ................................................................... 38-1

Saburo Muroga .............................................................................................. 39-1 Kazuo Yano and Saburo Muroga........................................................ 40-1

Naofumi Takagi, Haruyuki Tago, Charles R. Baugh and Saburo Muroga ........................................................................................................ 41-1 Naofumi Takagi, Charles R. Baugh and Saburo Muroga ............................... 42-1

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43

Dividers

Naofumi Takagi and Saburo Muroga .............................................................. 43-1

44

Full-Custom and Semi-Custom Design

45

Programmable Logic Devices

46

Gate Arrays

47

Field-Programmable Gate Arrays

48

Cell-Library Design Approach

49

Comparison of Different Design Approaches

Saburo Muroga ........................................ 44-1

Saburo Muroga ......................................................... 45-1

Saburo Muroga ...................................................................................... 46-1

SECTION VI

Saburo Muroga .................................................. 47-1

Saburo Muroga ....................................................... 48-1 Saburo Muroga............................... 49-1

Memory, Registers and System Timing

50

System Timing

Baris Taskin, Ivan S. Kourtev and Eby G. Friedman .............................. 50-3

51

ROM/PROM/EPROM

52

SRAM

53

Embedded Memory

54

Flash Memories

55

Dynamic Random Access Memory

56

Content-Addressable Memory Chi-Sheng Lin and Bin-Da Liu ............................................................................................................. 56-1

57

Low-Power Memory Circuits

Jen-Sheng Hwang ................................................................. 51-1

Yuh-Kuang Tseng ............................................................................................ 52-1 Chung-Yu Wu .......................................................................... 53-1

Rick Shih-Jye Shen, Frank Ruei-Ling Lin, Amy Hsiu-Fen Chou, Evans Ching-Song Yang and Charles Ching-Hsiang Hsu .............................................................................................. 54-1

SECTION VII

Kuo-Hsing Cheng............................................. 55-1

Martin Margala ........................................................ 57-1

Analog Circuits

58

Nyquist-Rate ADC and DAC

Bang-Sup Song .......................................................... 58-3

59

Oversampled Analog-to-Digital and Digital-to-Analog Converters John W. Fattaruso and Louis A. Williams III ...................................................................... 59-1

60

RF Communication Circuits

61

PLL Circuits

62

Switched-Capacitor Filters

Michiel Steyaert, Wouter De Cock and Patrick Reynaert .............................................................................. 60-1 Muh-Tian Shiue and Chorng-kuang Wang ............................................... 61-1 Andrea Baschirotto ......................................................... 62-1

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SECTION VIII

Microprocessor and ASIC

63

Timing and Signal Integrity Analysis Abhijit Dharchoudhury, David Blaauw and Shantanu Ganguly .............................................................................. 63-3

64

Microprocessor Design Verification

65

Microprocessor Layout Method

66

Architecture

67

Logic Synthesis for Field Programmable Gate Array (FPGA) Technology John Lockwood .............................................................. 67-1

SECTION IX

Vikram Iyengar............................................... 64-1

Tanay Karnik........................................................ 65-1

Daniel A. Connors and Wen-mei W. Hwu ................................................ 66-1

Testing of Digital Systems

68

Design for Testability and Test Architectures Dimitri Kagaris, Nick Kanopoulos and Spyros Tragoudas ............................................................................ 68-3

69

Automatic Test Pattern Generation

70

Built-In Self-Test

SECTION X

Spyros Tragoudas ............................................. 69-1

Dimitri Kagaris ............................................................................. 70-1

Compound Semiconductor Integrated Circuit Technology

71

Compound Semiconductor Materials

72

Compound Semiconductor Devices for Analog and Digital Circuits Donald B. Estreich .................................................................... 72-1

73

Compound Semiconductor RF Circuits

74

High-Speed Circuit Design Principles

SECTION XI

Stephen I. Long ........................................... 71-3

Donald B. Estreich ................................... 73-1 Stephen I. Long ........................................... 74-1

Design Automation

75

Internet-Based Micro-Electronic Design Automation (IMEDA) Framework Moon Jung Chung and Heechul Kim ........................................................ 75-3

76

System-Level Design Alice C. Parker, Yosef Tirat-Gefen and Suhrid A. Wadekar ......................................................................................................... 76-1

77

Performance Modeling and Analysis Using VHDL and SystemC Robert H. Klenke, Jonathan A. Andrews and James H. Aylor ................................................ 77-1

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xx

Table of Contents

78

Embedded Computing Systems and Hardware/Software Co-Design Wayne Wolf ............................................................................................. 78-1

79

Design Automation Technology Roadmap Donald R. Cottrell .......................................................................................................... 79-1

SECTION XII

VLSI Signal Processing

80

Computer Arithmetic for VLSI Signal Processing Earl E. Swartzlander, Jr. .................................................................................................. 80-5

81

VLSI Architectures for JPEG 2000 EBCOT: Design Techniques and Challenges Yijun Li and Magdy Bayoumi ............................................................ 81-1

82

VLSI Architectures for Forward Error-Control Decoders Arshad Ahmed, Seok-Jun Lee, Mohammad Mansour and Naresh R. Shanbhag ....................................................................................................... 82-1

83

An Exploration of Hardware Architectures for Face Detection T. Theocharides, C. Nicopoulos, K. Irick, N. Vijaykrishnan and M.J. Irwin ..................................................................................................................... 83-1

84

Multidimensional Logarithmic Number System Roberto Muscedere, Vassil S. Dimitrov and Graham A. Jullien .......................................................................... 84-1

SECTION XIII

Design Languages

85

Languages for Design and Implementation of Hardware Zainalabedin Navabi ...................................................................................................... 85-3

86

System Level Design Languages Shahrzad Mirkhani and Zainalabedin Navabi ...................................................................................................... 86-1

87

RT Level Hardware Description with VHDL Mahsan Rofouei and Zainalabedin Navabi ...................................................................................................... 87-1

88

Register Transfer Level Hardware Description with Verilog Zainalabedin Navabi ...................................................................................................... 88-1

89

Register-Transfer Level Hardware Description with SystemC Shahrzad Mirkhani and Zainalabedin Navabi ................................................................... 89-1

90

System Verilog

91

VHDL-AMS Hardware Description Language Naghmeh Karimi and Zainalabedin Navabi ...................................................................................................... 91-1

Saeed Safari ...................................................................................... 90-1

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92

Verification Languages

Hamid Shojaei and Zainalabedin Navabi................................ 92-1

93

ASIC and Custom IC Cell Information Representation Naghmeh Karimi and Zainalabedin Navabi ...................................................................... 93-1

94

Test Languages

95

Timing Description Languages Naghmeh Karimi and Zainalabedin Navabi ...................................................................................................... 95-1

96

HDL-Based Tools and Environments

Shahrzad Mirkhani and Zainalabedin Navabi ...................................... 94-1

Saeed Safari ................................................ 96-1

Index...................................................................................................................................... I-1

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Section I VLSI Technology John Choma, Jr. University of Southern California

0-8493-XXXX-X/04/$0.00+$1.50 © 2006 by CRC Press LLC

Section I-1

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1 Bipolar Technology B. Gunnar Malm Royal Institute of Technology

Jan V. Grahn

1.1 1.2

CONTENTS Introduction ...............................................................1-3 Bipolar Process Design ..............................................1-5 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7

Royal Institute of Technology

Mikael Östling Royal Institute of Technology

1.3

Figures of Merit ............................................................... 1-5 Process Optimization....................................................... 1-5 Vertical Structure ............................................................. 1-6 Collector Region .............................................................. 1-7 Base Region ...................................................................... 1-8 Emitter Region ................................................................. 1-9 Horizontal Layout ............................................................ 1-9

Conventional Bipolar Technology ..........................1-11 1.3.1 Junction-Isolated Transistors......................................... 1-11 1.3.2 Oxide-Isolated Transistors............................................. 1-11 1.3.3 Lateral pnp Transistors .................................................. 1-13

1.4

High-Performance Bipolar Technology..................1-13 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5

1.5

Polysilicon Emitter Contact........................................... 1-13 Advanced Device Isolation ............................................ 1-14 Self-Aligned Structures .................................................. 1-15 Single-Poly Structure ..................................................... 1-15 Double-Poly Structure ................................................... 1-17

Advanced Bipolar Technology.................................1-17 1.5.1 1.5.2 1.5.3 1.5.4

Implanted Base ............................................................... 1-19 Epitaxial Base.................................................................. 1-19 Bipolar Integration on SOI ........................................... 1-20 Future Trends ................................................................. 1-21

Acknowledgments .............................................................1-21 References ..........................................................................1-21

1.1 Introduction The development of a bipolar technology for integrated circuits (ICs) went hand in hand with the steady improvement in semiconductor materials and discrete components during the 1950s and 1960s. Consequently, silicon bipolar technology formed the basis for the IC market during the 1970s. As circuit dimensions shrink, the MOSFET (or MOS) has gradually taken over as the major technological platform for silicon ICs. The main reasons are the ease of miniaturization and high yield for MOS compared with bipolar technology. For VLSI circuits the low standby power of complementary MOS (CMOS) gates is a significant advantage compared with integrated bipolar circuits. The evolution of MOS technology has followed the famous Moore’s law that predicts a steady decrease in gate length. Bipolar technology has also benefited from the progress in lithography and is currently fabricated using deep UV tools with feature sizes close to 100 nm. The scaling has led to a © 2006 by CRC Press LLC

1-3

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The VLSI Handbook

significant performance improvement and is further illustrated in Figure 1.1, where the reported gate delay time for emitter coupled logic (ECL) and current mode logic (CML) circuits is plotted for a 10-year period. In addition to the reduced dimensions, the introduction of SiGe epitaxy for the base region has further pushed the performance limits. SiGe bipolars are now considered a mature technology and is mainly offered as a high-speed complement to the low-power MOS in the so-called BiCMOS technology. By adding a small amount of carbon to the SiGe epitaxial base, better profile control and compatibility with MOS process flows have been obtained [1]. A mature Si bipolar technology with implanted base at the 0.25 µm MOS technology node offers 12 ps gate delay and can be used to realize 10 Gb/s ICs [2]. The continuous performance increase owing to reduced dimension is illustrated in Table 1.1, where several generations of a commercial BiCMOS technology are compared [3]. As the dimensions are reduced, the traditional local oxidation of silicon (LOCOS) isolation technology is replaced by shallow and deep trenches to increase the packing density, and also to optimize the process flow by getting a more planar structure. As seen in the table, the epitaxial SiGe base markedly improves the device performance at the same technology node. Apart from high-speed performance, the bipolar transistor is recognized by its excellent analog properties which feature high linearity, superior low- and high-frequency noise behavior as well as very high transconductance [4]. Such properties are highly desirable for many RF applications, both for narrowband and broad-band circuits [5]. The high current drive capability per unit silicon area makes the bipolar transistor suitable for input/output stages in many IC designs (e.g., in fast SRAMs). The disadvantage of bipolar technology is the low transistor density, combined with large power dissipation.

ECL/CML gate delay time (ps)

30

20 15 10 5 0

FIGURE 1.1

Si implanted base SiGe epibase SiGeC epibase

25

1995

2000 Year

2005

Reported gate delay time for bipolar ECL and CML circuits versus year.

TABLE 1.1 Technology Evolution and Performance Trends of Commercial BiCMOS Technologies Si Implanted Base Emitter lithography (µm) fT (GHz) fMAX (GHz)s

1.0 13

Isolation CMOS gate length (µm) Metal layers

0.7 20

SiGe Epibase

0.5 30 60

0.25 40 90

0.42 4

0.14 5/6

LOCOS 0.78 3

0.70 3

0.25 70 >100 STI/DTI 0.14 5/6

Source: Modified from Deixler P. et al., IEEE Bipolar/BiCMOS Circuits Technol. Meeting Tech. Dig., 201, 2002. © 2006 by CRC Press LLC

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Bipolar Technology

1-5

High-performance bipolar circuits are therefore normally fabricated at a modest integration level (MSI/LSI). By using BiCMOS design, the benefits of both MOS and bipolar technology are utilized [6]. One example is mixed analog/digital systems, where a high-performance bipolar process is integrated with high-density CMOS [7]. This technology forms a vital part in several system-on-a-chip designs for telecommunication and wireless circuits. In this chapter, a brief overview of bipolar technology is given with an emphasis on the integrated silicon bipolar transistor. The information presented here is based on the assumption that the reader is familiar with bipolar device fundamentals and basic VLSI process technology. Bipolar transistors are treated in detail in well-known textbooks by Ashburn [8] and Roulston [9]. Section 1.2 will outline the general concepts in bipolar process design and optimization. Three generations of integrated devices representing state-of-the-art bipolar technologies for the 1970s, 1980s, and 1990s will be presented in Sections 1.3, 1.4, and 1.5, respectively. Finally, some future trends in bipolar technology are outlined.

1.2 Bipolar Process Design The design of a bipolar process starts with the specification of the application target and its circuit technology (digital or analog). This leads to a number of requirements formulated in device parameters and associated figures of merit. These are mutually dependent, and a parameter trade-off must therefore be made, making the final bipolar process design a compromise between various conflicting device requirements.

1.2.1 Figures of Merit In the digital bipolar process, the cutoff frequency (fT) is a well-known figure of merit for speed. The fT is defined for a common-emitter configuration with its output short circuit when extrapolating the small signal current gain to unity. From a circuit perspective, a more adequate figure of merit is the gate delay time (td) measured for a ring-oscillator circuit containing an odd number of inverters [10]. The td can be expressed as a linear combination of the incoming time constants weighted by a factor determined by the circuit topology (e.g., ECL) [10, 11]. Alternative expressions for td calculations have been proposed [12]. Besides speed, power dissipation can also be a critical issue in densely packed bipolar digital circuits, resulting in the power-delay product as a figure of merit [13]. In the analog bipolar process, the DC properties of the transistor are of utmost importance. This involves minimum values on common-emitter current gain (β), Gummel plot linearity (βmax/β) breakdown voltage (BVCEO), and early voltage (VA). The product β × VA is often introduced as a figure of merit for the device DC characteristics [14]. Rather than f T , the maximum oscillation frequency FMAX = FT (8π RBC BC ), is preferred as a figure of merit in high-speed analog design, where RB and CBC denote the total base resistance and the base-collector capacitance, respectively [15]. Alternative figures of merit for speed have been proposed in the literature [16, 17]. Analog bipolar circuits are often crucially dependent on a certain noise immunity, leading to the introduction of the corner frequency and noise figure as figures of merit for low-frequency and high-frequency noise properties, respectively [18].

1.2.2 Process Optimization The optimization of the bipolar process is divided between the intrinsic and extrinsic device design. This corresponds to the vertical impurity profile and the horizontal layout of the transistor, respectively [10]; see example in Figure 1.2, where the device cross section is also included. It is clear that the vertical profile and horizontal layout are primarily dictated by the given process and lithography constraints, respectively. Figure 1.3 shows a simple flowchart of the bipolar design procedure. Starting from the specified DC parameters at a given bias point, the doping profiles can be derived. The horizontal layout must be adjusted for minimization of the parasitics. A (speed) figure of merit can then be calculated. An implicit relation is thus obtained between the figure of merit and the processing parameters [11, 19]. In practice, © 2006 by CRC Press LLC

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The VLSI Handbook

(a)

E

B

C

Metal

(b) E

B

C

Oxide p

n


n


nepi n
p

Doping concentration (cm3)

(c)

n


1020

Emitter 1019 1018

Base Collector

1017

n


p 1016 1015

n epi 0

1

2

3 4 Depth (␮m)

5

6

FIGURE 1.2 (a) Layout, (b) cross section, and (c) example of impurity profile through emitter window for an integrated bipolar transistor (E, emitter; B, base; C, collector).

several iterations must be performed in the optimization loop to find an acceptable compromise between the device parameters. This procedure is substantially alleviated by one- or two-dimensional process simulations of the device fabrication as well as finite-element physical device simulations of the bipolar transistor [20, 21]. For optimization of a large number of device parameters, the strategy is based on screening out the unimportant factors, combined with a statistical approach (e.g., response surface methodology) [22, 23].

1.2.3 Vertical Structure The engineering of the vertical structure involves the design of the collector, base, and emitter impurity profiles. In this respect, fT is an adequate parameter to optimize. For a modern bipolar transistor with suppressed parasitics, the maximum fT is usually determined by the forward transit time of minority carriers through the intrinsic component. The most important fT trade-off is against BVCEO , as stated by the Johnson limit for silicon transistors [24], the product fT × BVCEO cannot exceed 200 GHz V. A more detailed calculation taking into account realistic doping profile predicts values of >500 GHz V) [25]. In © 2006 by CRC Press LLC

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1-7

Bipolar Technology

Start

BVCEO

IC

␤, VA

CIRCUIT REQUIREMENTS

J Epi thickness

NC

VERTICAL PROFILE

NB Emitter width HORIZONTAL LAYOUT x length

RC parasitics

fT, fmax, ␶d

Circuit topology weighting

Feedback

FIGURE 1.3

Generic bipolar device optimization flowchart.

fact, recent experimental results for high-speed SiGeC bipolar transistors have shown a value of 510 GHz V for a 300 GHz fT technology with 1.7 V BVCEO [26].

1.2.4 Collector Region The vertical n-type collector of the bipolar device in Figure 1.2 consists of two regions below the p-type base diffusion: a low or moderately doped n-type epitaxial (epi) layer, followed by a highly doped n+ subcollector. The thickness and doping level of the subcollector are noncritical parameters; a high arsenic or antimony doping density between 1019 and 1020 cm–3 is representative, resulting in a sheet resistance of 20–40 Ω/sq. In contrast, the design of the epilayer constitutes a fundamental topic in bipolar process optimization. To first-order, the collector doping in the epilayer is determined by the operation point (more specifically, the collector current density) of the component (see Figure 1.3). A normal condition is to have the operation point corresponding to maximum fT, which typically means a collector current density of the order of 2–4 × 104 A/cm2. As will be recognized later, bipolar scaling results in increased collector current densities. Above a certain current level, there will be a rapid roll-off in current gain and cutoff frequency. This is due to high-current effects, primarily the base pushout or Kirk effect, leading to a steep increase in the forward transit time [27]. Since the critical current value is proportional to the collector doping [28], a minimum impurity concentration for the epilayer is required, thus avoiding fT degradation (typically around 1017 cm–3 for a high-speed device). Usually, the epilayer is doped only in the intrinsic structure by a selectively implanted collector (SIC) procedure [29]. An example of such a doping profile from an advanced 0.25 µm BiCMOS technology is seen in Figure 1.4. Such a collector design permits an improved control over the base-collector junction, that is, shorter base width as well as suppressed Kirk effect. The high collector doping concentration, however, may be a concern for both CBC and BVCEO . The latter value will therefore often set a higher limit on the collector doping value. The SIC technology provides a simple way of creating a high-BVCEO device by masking the implantation. The reduced collector doping in the SIC-free device will also reduce the pinch-base resistance and CBC, which is in favor of high fmax [3]. © 2006 by CRC Press LLC

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The VLSI Handbook

Concentration (atoms/cm3)

1021 Phosphorus Boron Arsenic

1020 1019 1018 1017 1016 0.0

0.2

0.4 Depth (␮m)

0.6

0.8

FIGURE 1.4 Vertical impurity doping profile with a SIC for a 50 GHz fT/fmax Si-bipolar/BiCMOS technology (from Malm, B. G. et al., IEEE Trans. Electron Dev. vol. 52, 1423, 2005).

The preferred profile to achieve a good compromise between a too high field at the base-collector junction and suppression of the Kirk effect at high current densities is obtained by a retrograde collector profile [30]. For this profile the SIC implantation energy is chosen to obtain a low impurity concentration near the base-collector junction and then increasing toward the subcollector. The thickness of the epilayer exhibits large variations among different device designs, extending several micrometers in depth for analog bipolar components, whereas a high-speed digital design typically has an epilayer thickness around 1 µm or below, thus reducing the total collector resistance. As a result, the transistor breakdown voltage is sometimes determined by reach-through breakdown (i.e., full depletion of penetration of the epicollector). The thickness of the collector layer can therefore be used as a parameter in determining BVCEO , which in turn is traded off against fT . In cases where fmax is of interest, the collector design must be carefully taken into account. Compared with fT , the optimum fmax is found for thicker and less doped collector epilayers [32, 33]. The vertical collector design will therefore, to a large extent, determine the trade-off between fT and fmax.

1.2.5 Base Region The width and peak concentration of the base profile are two of the most fundamental parameters in vertical profile design. In a conventional Si bipolar process the base width is limited by the implantation energy and to some extent the collector doping, since an implanted profile will have a Gaussian tail toward the collector. The base width WB is normally in the range 0.1–1 µm, whereas a typical base peak concentration lies between 1017 and 1018 cm–3. In contrast to this, base widths of get_proc_type()); if(/*1st_line*/string_temp=="mixed") { SC_THREAD(mixed_behav); //only make the relevant behavior a thread! hardware_compute=new refined_computation("name",proc_num); //may need to add an argument this class... }

FIGURE 77.58 Refined computation part of processor model constructor. class rng_comp_tb : public sc_foreign_module { public: sc_in start; sc_out done; rng_comp_tb(sc_module_name nm, const char* hdl_name) : sc_foreign_module(nm, hdl_name), start("start"), done("done") { //cout '0'); elsif ld = '1' then q_t := d; elsif l_r = '1' then q_t := q_t (2 downto 0) & s_in ; else q_t := s_in & q_t (3 downto 1); end if; end if; q